1. Technical Field
Various embodiments generally relate to a semiconductor integrated circuit, and more particularly, to a phase splitter.
2. Related Art
A semiconductor integrated circuit apparatus may require signals having a predetermined phase difference, and include a phase splitter configured to split the phase of an input signal such that the split signals have the predetermined phase difference.
Referring to FIG. 1, the conventional phase splitter 1 may include delay circuits 11 to 13 composed of N(N is integer) inverters, delay circuits 14 and 15 composed of (N−1) inverters, and an RC delay circuit 16.
an input signal IN is passed through the delay circuits 11 to 13, a first phase signal OUT1 is generated.
Furthermore, as the input signal IN is passed through the delay circuits 14 and 15 and the RC delay circuit 16, an inverted signal of the first phase signal OUT1, that is, a second phase signal OUT2 having a phase difference of 180 degrees from the first phase signal OUT1 is generated.
The number of inverters forming the delay circuits 11 to 13 is different by 1 from the number of inverters forming the delay circuits 14 and 15 such that the signal generated by the delay circuits 11 to 13 has an inverted phase from the signal generated by the delay circuits 14 and 15.
Therefore, the RC delay circuit 16 is included to match a phase difference between the first and second phase signals OUT1 and OUT2.
However, while the inverter 11 for generating the first phase signal OUT1 has a fan-out of 1, the inverter 14 for generating the second phase signal OUT2 has a fan-out of 1 based on the inverter 15 and a fan-out of α based on the RC delay circuit, that is, a fan-out of (1+α).
Therefore, in the conventional phase splitter 1, the duty rates of the first and second phase signals OUT1 and OUT2 may be changed by the RC delay circuit 16, depending on a process, voltage, and temperature (PVT) variation.